Silicon Labs /Series0 /EZR32WG /EZR32WG230F256R63 /DMA /CHENC

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Interpret as CHENC

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CH0ENC)CH0ENC 0 (CH1ENC)CH1ENC 0 (CH2ENC)CH2ENC 0 (CH3ENC)CH3ENC 0 (CH4ENC)CH4ENC 0 (CH5ENC)CH5ENC 0 (CH6ENC)CH6ENC 0 (CH7ENC)CH7ENC 0 (CH8ENC)CH8ENC 0 (CH9ENC)CH9ENC 0 (CH10ENC)CH10ENC 0 (CH11ENC)CH11ENC

Description

Channel Enable Clear Register

Fields

CH0ENC

Channel 0 Enable Clear

CH1ENC

Channel 1 Enable Clear

CH2ENC

Channel 2 Enable Clear

CH3ENC

Channel 3 Enable Clear

CH4ENC

Channel 4 Enable Clear

CH5ENC

Channel 5 Enable Clear

CH6ENC

Channel 6 Enable Clear

CH7ENC

Channel 7 Enable Clear

CH8ENC

Channel 8 Enable Clear

CH9ENC

Channel 9 Enable Clear

CH10ENC

Channel 10 Enable Clear

CH11ENC

Channel 11 Enable Clear

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